Docs / Hardware

Hardware support

A per-target breakdown of what Prescaler supports today, so you know exactly what to expect before you start a project.

Getting started

  1. Pick a target

    Open the project wizard and choose a supported target from the catalog below, or start with the STM32F405 reference platform.

  2. Connect hardware, or skip it

    Plug in a supported probe, or launch the STM32F405 demo in QEMU with no hardware at all.

  3. Build and flash

    For CMake-supported targets, the wizard generates a ready-to-build project with a linker script and register definitions.

  4. Debug with full context

    Step through code with live peripheral registers, variables, and (where supported) RTOS task state.

Overview

STM32F405 is our reference platform: full QEMU simulation, a complete register database, and verified FreeRTOS task inspection out of the box. Every target in the catalog ships with register data, and CMake-supported targets can generate a ready-to-build project through the wizard. ESP32 register data is available for the Peripheral Browser and AI grounding, but its build and flash path is not wired into Prescaler. Eight targets have been build-tested against the real toolchain, and two have boot confirmation under QEMU. See each target's status below rather than assuming uniform support.

Core

Cortex-M4

Flash / RAM

1024 KB / 192 KB (128 + 64 CCM)

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

Yes, netduino2 machine

RTOS

FreeRTOS

CCM RAM is available through a dedicated linker section. Place a variable there with __attribute__((section(".ccmram"))).

Core

Cortex-M4

Flash / RAM

512 KB / 128 KB

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

Booted on netduinoplus2 (F405/F407-class, not an exact F411 match)

RTOS

FreeRTOS

GDB-confirmed boot and loop execution. UART output was not verified. Not run on real F411 hardware.

Core

Cortex-M3

Flash / RAM

64 KB / 20 KB

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

Attempted on stm32vldiscovery (F100 value-line, not an exact F103 match): faulted early during startup, cause not isolated

RTOS

FreeRTOS

The tightest RAM budget in the catalog at 20 KB. Plan FreeRTOS heap allocation accordingly.

Core

Cortex-M7

Flash / RAM

2048 KB / 1024 KB

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

No QEMU machine exists for H743

RTOS

FreeRTOS

The generated linker script uses a single flash and RAM region. Dual-bank flash and D1/D2 domain configuration can be added manually for advanced use cases. Power-domain and clock-tree setup has not been cross-checked against ST's reference manual.

Core

Cortex-M4

Flash / RAM

1024 KB / 256 KB

Probes

J-Link, CMSIS-DAP

QEMU

No QEMU machine exists for any nRF52 part

RTOS

FreeRTOS

ST-Link does not support Nordic devices. Use J-Link or CMSIS-DAP.

Core

Cortex-M7

Flash / RAM

1024 KB / 320 KB

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

No QEMU machine exists for STM32F7

RTOS

FreeRTOS

Reuses F405/F411's AHB1/APB1 peripheral map (same F4-family layout). The generated linker script models a single RAM region, not the real ITCM/DTCM split. Confirmed compiling and linking both as a standalone demo and through the IDE's own wizard output.

Core

Cortex-M4

Flash / RAM

1024 KB / 128 KB

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

No QEMU machine exists for STM32L4

RTOS

FreeRTOS

GPIO lives on AHB2, not AHB1 like F4/F7, and USART uses the modern CR1/ISR/TDR layout shared with G0, not F4's SR/DR style, both confirmed against the real SVD. The generated linker script models a single RAM region, not the real SRAM1/SRAM2 split. Confirmed compiling and linking both as a standalone demo and through the IDE's own wizard output.

Core

Cortex-M0+

Flash / RAM

64 KB / 8 KB

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

No QEMU machine exists for STM32G0

RTOS

Not available on this target

8 KB RAM is tighter than F103's 20 KB, so FreeRTOS isn't offered here, the same reasoning as AVR's 2 KB rather than F103's 20 KB. Confirmed compiling and linking both as a standalone demo and through the IDE's own wizard output.

Core

Cortex-M0+

Flash / RAM

256 KB / 32 KB

Probes

CMSIS-DAP, J-Link

QEMU

No QEMU machine exists for SAMD21

RTOS

Not available on this target yet

Covers Arduino Zero/MKR/M0 boards. A genuinely different peripheral model from the ST/Nordic parts elsewhere in the catalog: clock gating goes through PM's APBx mask registers, and GPIO is grouped (PORTA/PORTB) rather than one block per port letter, both confirmed against the real SVD. GPIO/clock-gating scope only, no UART yet, SAMD21's SERCOM pin-muxing needs its own research pass. Confirmed compiling and linking both as a standalone demo and through the IDE's own wizard output.

Core

Cortex-M4

Flash / RAM

512 KB / 64 KB

Probes

J-Link, CMSIS-DAP

QEMU

No QEMU machine exists for any nRF52 part

RTOS

FreeRTOS

ST-Link does not support Nordic devices. Use J-Link or CMSIS-DAP. Confirmed compiling and linking both as a standalone demo and through the IDE's own wizard output.

Core

Cortex-M4

Flash / RAM

1024 KB / 192 KB (128 + 64 CCM)

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

No QEMU machine specific to F407 (F405's netduino2 emulates an M3 core, not this part)

RTOS

FreeRTOS

Shares the same stm32f4x OpenOCD target family and SVD-derived register layout as the verified F405 above, but this exact part hasn't been individually compiled, flashed, or booted in-house.

Core

Cortex-M0+

Flash / RAM

128 KB / 36 KB

Probes

ST-Link, J-Link, CMSIS-DAP

QEMU

No QEMU machine exists for STM32G0

RTOS

Not available on this target

Shares the same stm32g0x OpenOCD target family as the build-verified G031 above, with more flash/RAM headroom, but this exact part hasn't been individually compiled, flashed, or booted in-house.

Core

Dual Cortex-M0+ (silicon spec)

Flash / RAM

2048 KB / 264 KB

Probes

CMSIS-DAP

QEMU

Coming in a future release

RTOS

Not available on this target

The chip has two cores, but Prescaler only generates single-core bring-up today, no core1 support and no RTOS option for RP2040. QEMU simulation is on our roadmap.

Core

Xtensa LX6 (dual core)

Flash / RAM

4096 KB / 520 KB

Probes

External JTAG

QEMU

Not currently available

RTOS

FreeRTOS, included with ESP-IDF

Register data ships for this chip (Espressif's own SVD, the same source every other catalog chip's register data comes from), so the Peripheral Browser and register-grounded AI answers work once a project targeting it is open. Build and flash are not wired up yet: build through the ESP-IDF toolchain (idf.py) manually, flash manually with idf.py flash. Debugging requires an external JTAG probe, classic ESP32 doesn't include the built-in USB-JTAG found on newer S3/C3 variants.

Planned, not in the catalog

In the works, not in the catalog yet

These are chips we've researched and want to add, not chips you can select in the wizard today. Each line is a real finding from checking toolchain and register-data availability, not a guess.

  • ESP32-S3 / ESP32-C3Toolchain not available in our current build environment

    These are the ESP32 variants people actually reach for now (the catalog's ESP32-WROOM-32 entry is the older plain part). Adding them needs the full ESP-IDF SDK (Xtensa toolchain for S3, RISC-V toolchain for C3), which is a large, separate install, not just a compiler. Not started.

  • SAMD51Toolchain and register data confirmed available, not yet built

    SAMD21 (Arduino Zero/MKR/M0, GPIO/clock-gating only) is now in the catalog as build-verified. SAMD51 (Cortex-M4, used in higher-end SAMD boards) uses a further-revised clock system (MCLK instead of PM) and hasn't been started yet.

  • Teensy 4.x (i.MX RT1062)Toolchain and register data confirmed available, not yet built

    Popular in higher-performance maker and pro-hobbyist work. arm-none-eabi-gcc supports the core, and NXP's SVD data exists. The blocker: this chip has no on-chip flash, it boots from external QSPI NOR through FlexSPI, which needs a bootloader-aware linker script unlike anything else in the catalog today. Not started.

  • ATmega328P (Arduino Uno)No SVD available; hardware debugging needs extra tooling regardless of ours

    AVR isn't ARM, so it has no CMSIS-SVD register data the way every catalog chip today does; register access there is normally done through avr-libc header definitions instead. The toolchain (avr-gcc, avrdude) is straightforward, but live hardware debugging needs debugWIRE-capable programming hardware and a board modification most Arduino Uno setups don't have, a limitation of the chip itself, not something we can build around. A flash-only path (avrdude, no live debug) is realistic; full debug parity with the rest of the catalog isn't. Not started.

Requesting a new target

ESP32-WROOM-32 is now part of the catalog. See the roadmap above for what we're already researching, including Arduino Uno. Additional AVR variants (Mega2560, ATtiny) are next most requested beyond that.

Have a target you'd like to see supported? Open an issue on GitHub, that's also where we track hardware bugs and probe compatibility reports.

Open an issue on GitHub

Related: Whitepaper · Billing and credits